A CMOS On-Chip High-Precision PVTL Detector

A novel PVTL (Process, Voltage, Temperature, Leakage) detection circuit consisting of four individual detectors is proposed in the investigation. Voltage Variation Detector is composed of a feedback control block comprising multi-stage delay cells using high Vth devices such that 0.5% of VDD variation can be detected. Temperature Detector based on a current to pulse converter is proved to attain high linearity of temperature sensing. PMOS Variation Detector and NMOS Variation Detector are carried out using threshold voltage sensors and ring oscillators, respectively. Thus, all process corners can be clearly di ﬀ erentiated using pulse counts. Leakage Detector is realized by a single-MOSFET leakage current detector. Most of prior leakage detectors compensate for leakage current instead of detecting the precise amount of the leakage current. The proposed leakage detector, however, can accurately detect the leakage current of CMOS transistors, where a Strobe pulse generator is used as a detection switch. Thus, the detection time is predictable. It elevates the reliability of the detection result. The proposed PVTL detector design is implemented using a typical 180 nm CMOS process to justify the performance. Measurement shows that the proposed design is the best of all prior PVTL detectors in terms of accuracy.


Introduction
The transistors shrink in size as CMOS process advances, which benefits the digital circuits, including lower cost per area, lower supply voltage, lower power consumption, as well as higher operating speed. However, in semiconductor manufacturing, a 3-σ rule is required to overcome different doping concentrations on each N-type and P-type transistor, namely process corners, which might severely affect the performance of digital circuits. Meanwhile, as shown in Figure 1 [1], voltage and temperature are also unavoidable variations in any environment, which are needed to be detected to neutralize their effects on transistor operations. Moreover, the leakage issue becomes even more important by advancing of CMOS processes. Figure 2 shows the average gate leakage of different technology nodes, where the leakage increases as the process node evolves to ever-smaller devices [2], [3]. PVTL variations must be considered during chip design especially in digital circuits. To ensure the reliability of the performance, detections as well as auto-adjustments must be included in the system. Many prior PVTL detectors have been reported to address this problem with solutions [3]- [12]. A few other works reported to adjust for leakage problems [13]- [17]. Therefore, according to the challenges mentioned above, a highprecision detector for process, voltage, temperature, and leakage (PVTL) variation could be a solution. Figure 1: Acceptable envelope between with and without PVT detection [1] In this investigation, high precision P, V, T, and L detectors are proposed, respectively. The proposed Voltage Variation Detector is featured with a delay line composed of high-Vth MOS-based delay cells. The proposed Temperature Detector consists of a temperaturesensitive current generator, a Charge and Discharge Circuit (CDC), and a Voltage Window Comparator (VWC). Lastly, the proposed process variation detectors comprises separate NMOS and PMOS process variation detectors such that all the possible process corners will be detected. Measurement given that the proposed corner detectors are realized using 0.18 micro meter CMOS technology node show that the voltage detecting resolution is as good as 0.5% of VDD, and temperature detecting resolution is proved to be 3 • C in [-40 • C, +80 • C], and all the process variations, (SS, SF, TT, FS, FF), are detectable. Moreover, the leakage of PMOS and NMOS can be exactly detected by Leakage Detector, respectively. FinFET 10000 Figure 2: Gate leakage of different technology nodes [2], [3] 2 High-precision PVTL detector Figure 3 shows the block diagram of the proposed on-chip highprecision PVTL detector contains the PMOS Variation Detector, NMOS Variation Detector, Temperature Detector, Voltage Variation Detector, and Leakage Detector. The details of each sub-circuit are given in the following text.

Voltage Variation Detector
The schematic of Voltage Variation Detector in Figure 3 is shown in Figure 4, consisting of a buffer delay line (BF1-BF6), DFFs (FF1-FF6), XORs, and a Controllable delay block. Notably, all the cells in this circuit is also driven by the same input voltage (VDD). The operation of this circuit is summarized as follows: • Due to the variation of input voltage (VDD), the delay generated by the buffer delay line will be varied accordingly.
• The generated codes at each delay cell are registered by corresponding DFFs, which are then the output of the adjacent DFF to generate Voltage code, V[0]-V [4].
• The last output of the buffer delay line, namely D6, is coupled to an input of Controllable delay block to form a feedback system.
Since Controllable delay block is meant to monitor the clock drift caused by voltage variation, the delay of each stage therein shall be auto-tuned by input voltage (VDD) and the final delay generated by the mentioned buffer delay line, e.g., D6. The schematic of the delay stage in Controllable delay block is revealed in Figure 5. It is notably featured with high Vth devices to prevent possible device parameter variation thanks to its thick gate oxide. D6 of buffer delay line is coupled to Vctrl+ and Vctrl-such that both the pull-up and pull-down switches have turned into a voltage controlled resistor.

Process Variation Detector
The schematics of PMOS Variation Detector and NMOS Variation Detector in Figure 3 are shown in Figure 6 and Figure 7, respectively. Two individual process variation detectors are required for PMOS and NMOS to find out all the possible process corners. Take the N-type process variation detector in Figure 6 as an example. Clock P is coupled from the system clock source to an NAND gate to trigger the ring oscillator composed of only NMOS delay stages. As shown in Figure 7, different pulse counts (11, 6, 2) are attained at the counter output given that NMOS are at F (fast), T (typical), S (slow) corners respectively, when Clock P is high.
As for PMOS process variation detector, because the pulse count generated by PMOS devices in different corners is small, the threshold voltage is used to judge the changes in different process corners. When the Clock P drops to low, MP17 in Figure 6 will be turned on and discharged to Vth of the PMOS. Similarly, MP18 will be discharged to twice Vth of the PMOS. The comparator is compared with the two bias voltages (vbias1 and vbias2) to determine the corner which it is now.

Temperature Detector
The block diagram of Temperature Detector in Figure 3 is shown in Figure 9, consisting of a Current Generator (CG), a Charge and Discharge Circuit (CDC), a Voltage Window Comparator (VWC), and an Encoder. The schematic of CG, CDC, and VWC is given in Figure 10. Current Generator is charge of generating a current highly correlated to temperature variation. The operation of CDC and VWC is summarized as follows: • Charging operation: The switch sw1 is shorted to node a1.
Then, the storage capacitor, cap, starts to be charged via saturated MP12.
• Discharging operation: As soon as the voltage of the cap, V cap (T), reaches VH, the output of VWC, V OUT (T), is switched low to short-circuit sw1 to node b1. MN13 is tuned on to be able to sink a current which is twice of the charging current provided by MP13. Thus, cap is discharged. As soon as the V cap (T) is pulled down to VL, V OUT (T) will be turned high to start another cycle of charging-and-discharging operation.

Leakage Detector
The schematic of Leakage Detector in Figure 3 is shown in Figure  12, consisting of a Strobe pulse generator, a Switch, two PMOS Leakage detectors, two NMOS Leakage detectors, a Voltage-tofrequency converter (VFC), and a Counter.  The operation of the proposed Leakage Detector is summarized as follows: • The Strobe pulse generator generates pulses which is the control signal of the four Leakage detectors and the Counter.
• Using the control signal Ctr and Ctrl[3:0] to select PMOS and NMOS with different aspect ratios as the object of leakage detection.
• The selected Leakage detector charges the capacitor with the leakage of a single PMOS or NMOS, and then converts the capacitor voltage output into a periodic square wave by the Voltage-to-frequency converter.
• The number of pulses of the periodic square wave is counted by Counter. If the larger the leakage is, the charging voltage of the capacitor will rise faster. Thus, the number of pulses registered in the counter will be higher. Figure 13 shows the schematic of a PMOS Leakage detector and the equivalent voltage source model, which is the same as a DC transient circuit for RC charging and discharging. The function of NMOS Leakage detector is similar.
where V R (t) is the voltage across the resistor, V C (t) is the capacitor voltage, V S is the supply voltage (VDD), and e is the natural logarithm. When the circuit current drops from the maximum value to 36.8 %, the time is the product of the resistance and the capacitance, so the time constant (τ) of the RC charging circuit is the product of resistance and capacitance, as shown in Eqn. (4).
Through the natural logarithmic function calculation, as shown in Eqn. (5) and (6), the time for the capacitor charging to be stable is 5τ, and then the resistance R is derived. Thus, referring to Eqn. (3) to derive the capacitor charging current at any time. In addition, the charging current would decrease by time. The initial PMOS leakage charging current I(0) is as shown in Eqn. (7).

Measurement and Verification
This proposed PVTL detector design is realized using TSMC 180 nm CMOS process. The layout and die photo of the entire PVTL detector are shown in Figure 14 (a) and (b), respectively, where the core area is 1156×1671 µm 2 , and the total chip area is 2493×2553 µm 2 . The chip measurement setup of the proposed design is shown in Figure 15. The chip is soldered on the PCB to reduce noise interference. The Power Supply Agilent E3631A provides the required voltages to the chip. Arbitrary Waveform Generator Agilent 33522A and Signal Generator provide the Clock V and Clock P , respectively. The Programmable Compact Temperature & Humidity System is the equipment to define the environment temperature. The oscilloscope WaveRunner610Zi is used to observe waveforms and check the circuit operations.  Figure 16 shows the measurement waveforms of the output signals of Voltage Variation Detector. It shows that Voltage code [4:0] is changed when VDD varies. The VDD is drifted by ±1%, ±0.5%, and 0%. Therefore, the measurement result proves the correctness of Voltage Variation Detector. Figure 17 shows the measurement waveforms of the output signals of Process Variation Detectors. It shows that the Process code is 0000 by all six chips. Thus, all PMOS and NMOS are made by SS corner. Notably, it is hard to ask foundry to deliberately fabricate the dies/chips at different process corners.

Temperature Detector
The interval between each measurement is at least an hour to ensure that the temperature of the entire chip and PCB is stable. Table 1 summarizes all the readings in the measurement, where the initial temperature is 20 • C, and the initial F OUT (T) is 206 kHz. By tuning Programmable Compact Temperature & Humidity System, the temperature and F OUT (T) rise continuously. In addition, F OUT (T) in measurement is lower than that given by the simulations due to the loading of the passive components and PCB. However, F OUT (T)-temperature curve is still linear in measurement. The error in Table 1 is calculated with the F OUT (T) by the linear regression. The maximum error is 2.24 % at -5 • C, while the overage error is 0.773 %.

Leakage Detector
Referring to the analysis of the pulse count and leakage current which is shown in Figure 18 and the measurement waveforms of Leakage Detector shown in Figure 19. Figure 19   www.astesj.com 91   Table 2 tabulates the performance comparison of several recent PVTL detector works. This work attain the best FOM b and the highest accuracy among all PVTL detector works in 2011-2020. However, due to the fact that four individual detectors are used, the proposed design pay the price of larger area. If the area is a factor be considered, FOM a , is also given and defined in Table 2. Apparently, it is a trade-off between high performance and large area.

Conclusion
A highly accurate on-chip PVTL detector design is demonstrated in this investigation, where four individual detectors are used to assist the quality improvement of chips implemented by CMOS. If the ICs' leakage and PVT corner are correctly estimated, the host controller will be able to perform better.

Acknowledgment
This work was partially supported by FocalTech Systems Co., Ltd, Taiwan