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Author/Affiliation: Arturo Sibaja-HernandezOpen AccessArticle
9 Pages, 1,504 KB 
On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials
Abstract:
In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate stack has reduced the Dit and Nbt below the target…
Read More(This article belongs to the SP5 (Special Issue on Multidisciplinary Sciences and Engineering 2018) & Section Electronic Engineering (EEE))