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Author/Affiliation: Samraj DaphniOpen AccessArticle
5 Pages, 1,597 KB 
Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications
Abstract:
The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In…
Read More(This article belongs to Section Electronic Engineering (EEE))