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Keyword: Dynamic powerOpen AccessArticle
7 Pages, 832 KB 
A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes
Abstract:
In advanced technologies nodes, starting from 28 nm to 7 nm and below, the power consumed of integrated circuits (ICs) becomes a big concern. Consequently, actual electronic design automation (EDA) tools are facing many challenges to have low power, reduced area and keep having required performance. To reach required success criteria, and because each picosecond…
Read More(This article belongs to the SP8 (Special Issue on Multidisciplinary Sciences and Engineering 2019-20) & Section Electronic Engineering (EEE))
Open AccessArticle
13 Pages, 3,747 KB
An FPGA Implementation of Resource-Optimized Dynamic Digital Beamformer for a Portable Ultrasound Imaging System
Abstract:
This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128- channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx…
Read More(This article belongs to the SP5 (Special Issue on Multidisciplinary Sciences and Engineering 2018) & Section Electronic Engineering (EEE))