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Keyword: VHDL
Design, Optimization and Simulation of a New Decoder for Reed Solomon and BCH Codes using the New Syndromes Block
In this paper, a new syndrome block for Reed Solomon RS and BCH codes used respectively in digital Video broadcasting DVB-S and DVB-S2 has been presented in order to reduce the number of iterations compared to the existed block, which can be found in the literature, the new method is based on a factorization of…
Read More FPGA-Based Homogeneous and Heterogeneous Digital Quantum Coprocessors
Quantum computers are heterogeneous device. It consists of a main CPU and a quantum accelerator. True quantum accelerator (or coprocessor) is analog and probabilistic device. Qubits are the basic building blocks of quantum computers. But qubits can be digital. A digital qubit is similar to RISC processor pipeline and is an unique chain of digital…
Read More FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters
This work presents new pipeline-parallel, generic and configurable parallel hardware architectures for the Direct/Inverse Wavelet Packet Transform (DWPT/IDWPT) independent of any specific family of wavelets, implemented in FPGA technology using a parallel architecture of direct FIR filter. We propose in the following paper, new P-parallel structures for the DWPT and IDWPT transforms based on the…
Read More Simulation and FPGA Implementation of a Ring Oscillator Sensor for Complex System Design
This paper, presents the design of a temperature sensor based on RO (Ring Oscillator) in order to make a thermal study for the detection and localization of thermal peaks in a complex system. In this work, a simulation and FPGA implementation of a fully digital temperature sensor features a number of exact inverters that can…
Read More A Novel Ultra High Speed and Configurable Discrete Wavelet Packet Transform Architecture
This work is dedicated to present a new pipeline-parallel architecture of Discrete Wavelet Packet Transform (DWPT) for all wavelet family implemented in FPGA technology. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. In this article, we propose two…
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