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Keyword: Xilinx
Hardware and Secure Implementation of Enhanced ZUC Steam Cipher Based on Chaotic Dynamic S-Box
Despite the development of the Internet and wired networks such as fiber optics, mobile networks remain the most used thanks to the mobility they offer to the user. However, data protection in these networks is more complex because of the radio channels they use for transmission. Hence,there is a need to find more sophisticated data…
Read More FPGA Implementation of 5G NR LDPC Codes
As a result of rising expectations for quality, the employment of advanced technical requirements for future fifth-generation (5G) new radio is required. The error-correction coding method is one of the most important components of a new generation. The 5G NR New Radio Low-Density Parity Check (LDPC) codes, which have been adopted by the 5G standard,…
Read More Modified Blockchain based Hardware Paradigm for Data Provenance in Academia
Educational organizations often need to distribute academic transcripts and certificates upon student’s request since they are mandatory for admission into new scholarly programs including placement activities. Manual procedures involved with the transmission process of academic document is indeed a tedious task that results in substantial overhead. Thus the necessity for an autonomous electronic system for…
Read More Design and Implementation of Reconfigurable Neuro-Inspired Computing Model on a FPGA
In this paper we design a large scale reconfigurable digital bio-inspired computing model. We consider the reconfigurable and event driven parameters in the developed field-programmable neuromorphic computing system. The various Intellectual Property (IP) cores are developed for the modules such as Block RAM, Differential Clock, Floating Point, and First In First Out (FIFO) for the…
Read More Design and Analysis of 32-bit Parallel Prefix Adders for Low Power VLSI Applications
The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In…
Read More Virtual Output Queues Architecture for High Throughput Data Center Nodes
The latest design approach for Data Centers (DCs) follows the direction of exploiting optical switching to connect Top-of-Rack (ToR) switches that serve thousands of data storing and computing devices. A ToR’s usual function is the Virtual Output Queues (VOQs), which is the prevalent solution for the head-of-line blocking problem of the DC switches. An effective…
Read More A New profiling and pipelining approach for HEVC Decoder on ZedBoard Platform
New multimedia applications such as mobile video, high-quality Internet video or digital television requires high-performance encoding of video signals to meet technical constraints such as runtime, bandwidth or latency. Video coding standard h.265 HEVC (High Efficiency Video Coding) was developed by JCT-VC to replace the MPEG-2, MPEG-4 and h.264 codecs and to respond to these…
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