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Author/Affiliation: Wei-Chih Chang
Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon
This investigation demonstrates the analysis of various layout arrangements for oscillator (OSC) realized by CMOS technologies. Moreover, the analysis reveals that the serpentine style of OSC stages attains the minimum output variation on silicon. This investigation is firstly verified by post-layout simulations, comparing the variation with different kinds of layout arrangement for OSC designs, including…
Read More A CMOS On-Chip High-Precision PVTL Detector
A novel PVTL (Process, Voltage, Temperature, Leakage) detection circuit consisting of four individual detectors is proposed in the investigation. Voltage Variation Detector is composed of a feedback control block comprising multi-stage delay cells using high Vth devices such that 0.5% of VDD variation can be detected. Temperature Detector based on a current to pulse converter…
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