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Keyword: FPGAFPGA Implementation of 5G NR LDPC Codes
As a result of rising expectations for quality, the employment of advanced technical requirements for future fifth-generation (5G) new radio is required. The error-correction coding method is one of the most important components of a new generation. The 5G NR New Radio Low-Density Parity Check (LDPC) codes, which have been adopted by the 5G standard,…
Read MoreA Survey of FPGA Robotics Applications in the Period 2010 – 2019
FPGAs constitute a flexible and increasingly popular controlling solution for robotic applications. Their core advantages regarding high computational performance and software-like flexibility make them suitable controller platforms for robots. These robotic applications include localization / navigation, image processing, industrial or even more complex procedures such as operating on medical or human assistant tasks. This paper…
Read MoreFPGA-Based Homogeneous and Heterogeneous Digital Quantum Coprocessors
Quantum computers are heterogeneous device. It consists of a main CPU and a quantum accelerator. True quantum accelerator (or coprocessor) is analog and probabilistic device. Qubits are the basic building blocks of quantum computers. But qubits can be digital. A digital qubit is similar to RISC processor pipeline and is an unique chain of digital…
Read MoreDesign and Implementation of Quad-Site Testing on FPGA Platform
As manufacturing efficiency has become a main focus of today’s business, it is very critical to surge the throughput by developing different test strategies. With throughput, testing cost also has been recognized as the major challenge in the future of leading semiconductors. Reducing test time is a significant effort to maximize throughput as the complexity…
Read MoreDesign and Implementation of Reconfigurable Neuro-Inspired Computing Model on a FPGA
In this paper we design a large scale reconfigurable digital bio-inspired computing model. We consider the reconfigurable and event driven parameters in the developed field-programmable neuromorphic computing system. The various Intellectual Property (IP) cores are developed for the modules such as Block RAM, Differential Clock, Floating Point, and First In First Out (FIFO) for the…
Read MoreFPGA Acceleration of Tree-based Learning Algorithms
Machine learning classifiers provide many promising solutions for data classification in different disciplines. However, data classification at run time is still a very challenging task for real-time applications. Acceleration of machine-learning hardware solutions is needed to meet the requirements of real-time applications. This paper proposes a new implementation of a machine learning classifier on Field…
Read MoreEmbedded Artificial Neural Network FPGA Controlled Cart
An artificial neural network (ANN) computing system can be significantly influenced by its implementation type. The software implemented ANN can produce high accuracy output with slow computation time performance compared to hardware implemented ANN which runs at a faster computation time but with low accuracy. Normally, software implementation reduces the proficiency and efficiency of the…
Read MoreFPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters
This work presents new pipeline-parallel, generic and configurable parallel hardware architectures for the Direct/Inverse Wavelet Packet Transform (DWPT/IDWPT) independent of any specific family of wavelets, implemented in FPGA technology using a parallel architecture of direct FIR filter. We propose in the following paper, new P-parallel structures for the DWPT and IDWPT transforms based on the…
Read MoreDesign of smart chess board that can predict the next position based on FPGA
The abilities of human brain to discover solutions for many problems is a great gift that motivate the scientists to develop the revolution of the artificial intelligence and using it in many areas. This paper proposed an intelligent chessboard which works in a way that similar to the human brain that predicts the next positions…
Read MoreAn FPGA Implementation of Resource-Optimized Dynamic Digital Beamformer for a Portable Ultrasound Imaging System
This paper presents a resource-friendly dynamic digital beamformer for a portable ultrasound imaging system based on a single field-programmable gate array (FPGA). The core of the ultrasound imaging system is a 128- channel receive beamformer with fully dynamic focusing embedded in a single FPGA chip, which operates at a frequency of 40 MHz. The Rx…
Read MoreSimulation and FPGA Implementation of a Ring Oscillator Sensor for Complex System Design
This paper, presents the design of a temperature sensor based on RO (Ring Oscillator) in order to make a thermal study for the detection and localization of thermal peaks in a complex system. In this work, a simulation and FPGA implementation of a fully digital temperature sensor features a number of exact inverters that can…
Read MoreHardware and Secure Implementation of Enhanced ZUC Steam Cipher Based on Chaotic Dynamic S-Box
Despite the development of the Internet and wired networks such as fiber optics, mobile networks remain the most used thanks to the mobility they offer to the user. However, data protection in these networks is more complex because of the radio channels they use for transmission. Hence,there is a need to find more sophisticated data…
Read MoreNatural Tsunami Wave Amplitude Reduction by Straits – Seto Inland Sea
Seto Inland Sea is situated between Japanese islands Honshu, Kyushu, and Shikoku. It is separated from the ocean by the Bungo Channel, Kii Channel, and other narrow straits around Shikoku Island. The objective of the article is to draw the attention to the question of how well the coastal population and infrastructure of those locations…
Read MoreSIFT Implementation based on LEON3 Processor
This paper proposes a new method of implementation of the part of SIFT (Scale-Invariant Feature Transform) algorithm used to extract the feature of an image of a size 256×256 of pixels, which is mainly based on the using the LEON3 soft core processor .With this method it is possible to detect points of interest and…
Read MoreModified Blockchain based Hardware Paradigm for Data Provenance in Academia
Educational organizations often need to distribute academic transcripts and certificates upon student’s request since they are mandatory for admission into new scholarly programs including placement activities. Manual procedures involved with the transmission process of academic document is indeed a tedious task that results in substantial overhead. Thus the necessity for an autonomous electronic system for…
Read MoreC-Band FMCW Radar Design and Implementation for Breathing Rate Estimation
In this paper, a portable Frequency Modulated Continuous Wave (FMCW) radar system was designed and implemented for human movements and breathing detection. The radar operates with a frequency band ranges from 4.7 to 4.9GHz. The radar sub-systems were designed and simulated using up to date computer-aided-design tools before implementation. The Voltage Controlled Oscillators (VCO), high…
Read MoreVirtual Output Queues Architecture for High Throughput Data Center Nodes
The latest design approach for Data Centers (DCs) follows the direction of exploiting optical switching to connect Top-of-Rack (ToR) switches that serve thousands of data storing and computing devices. A ToR’s usual function is the Virtual Output Queues (VOQs), which is the prevalent solution for the head-of-line blocking problem of the DC switches. An effective…
Read MoreSynthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates
Currently, synchronous digital circuits (SDC) may require certain design conditions, such as power consumption, robustness, performance, etc. These design conditions are more difficult to satisfy when SDC are implemented in VLSI (Very Large Scale Integration) technology and in the deep-sub-micron MOS (DSM-MOS) technology. The asynchronous design style has properties that serve as an alternative to…
Read MoreA Novel Ultra High Speed and Configurable Discrete Wavelet Packet Transform Architecture
This work is dedicated to present a new pipeline-parallel architecture of Discrete Wavelet Packet Transform (DWPT) for all wavelet family implemented in FPGA technology. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. In this article, we propose two…
Read MoreA Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation
Side-Channel Attack (SCA) is an effective method in extracting the secret key of cryptographic algorithms by correlating the physical leakage information with the processed data. In this paper, we propose an arithmetic hiding cum Look-up Table (AHLUT) based Substitution-Box (S-Box) in AES-128 cryptographic algorithm implementation to countermeasure against SCA. There are three key features in…
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