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Keyword: Frequency dividerOpen AccessArticle
6 Pages, 1,273 KB 
Stability and nonlinear controller design of Fast-Lock Phase-Locked Loop in 0.18-µm CMOS
Abstract:
This paper introduces a kind of novel backstepping phase- locked loops (PLL). The paper presents a developed theoretical model of (PLL) frequency synthesizer and provides analytical equations for calculating the desired specification such as phase margin (PM). The proposed model aims to improve the control accuracy, ensure stability and reducing the lock time. Adaptive controller…
Read More(This article belongs to the SP3 (Special issue on Recent Advances in Engineering Systems 2017) & Section Electronic Engineering (EEE))