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Keyword: Parallel-Pipeline ArchitectureOpen AccessArticle
12 Pages, 1,500 KB 
FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters
Abstract:
This work presents new pipeline-parallel, generic and configurable parallel hardware architectures for the Direct/Inverse Wavelet Packet Transform (DWPT/IDWPT) independent of any specific family of wavelets, implemented in FPGA technology using a parallel architecture of direct FIR filter. We propose in the following paper, new P-parallel structures for the DWPT and IDWPT transforms based on the…
Read More(This article belongs to the SP5 (Special Issue on Multidisciplinary Sciences and Engineering 2018) & Section Electronic Engineering (EEE))