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Keyword: VHDL-RTL modelingOpen AccessArticle
8 Pages, 2,463 KB 
A Novel Ultra High Speed and Configurable Discrete Wavelet Packet Transform Architecture
Abstract:
This work is dedicated to present a new pipeline-parallel architecture of Discrete Wavelet Packet Transform (DWPT) for all wavelet family implemented in FPGA technology. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. In this article, we propose two…
Read More(This article belongs to the SP3 (Special issue on Recent Advances in Engineering Systems 2017) & Section Electronic Engineering (EEE))