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Author/Affiliation: Yung-Yuan HoOpen AccessArticle
7 Pages, 6,496 KB 
Analysis of Layout Arrangement for CMOS Oscillators to Reduce Overall Variation on Silicon
Abstract:
This investigation demonstrates the analysis of various layout arrangements for oscillator (OSC) realized by CMOS technologies. Moreover, the analysis reveals that the serpentine style of OSC stages attains the minimum output variation on silicon. This investigation is firstly verified by post-layout simulations, comparing the variation with different kinds of layout arrangement for OSC designs, including…
Read More(This article belongs to Section Electronic Engineering (EEE))