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Keyword: CMOS Process
A CMOS On-Chip High-Precision PVTL Detector
A novel PVTL (Process, Voltage, Temperature, Leakage) detection circuit consisting of four individual detectors is proposed in the investigation. Voltage Variation Detector is composed of a feedback control block comprising multi-stage delay cells using high Vth devices such that 0.5% of VDD variation can be detected. Temperature Detector based on a current to pulse converter…
Read More Applications of TCAD Simulation Software for Fabrication and study of Process Variation Effects on Threshold Voltage in 180nm Floating-Gate Device
In this work, a study of the process variation effects on the threshold voltage of a floating- gate device is proposed. The study demonstrates the sensitivity of the threshold voltage to five geometrical parameters including gate length, gate width, tunneling gate oxide thickness, bottom oxide-nitride-oxide oxide thickness, and nitride spacer thickness. This paper also proposed…
Read More A High Efficiency 0.13μm CMOS Full Wave Active Rectifier with Comparators for Implanted Medical Devices
This paper presents a full wave active rectifier for biomedical implanted devices using a new comparator in order to reduce the rectifier transistors reverse current. The rectifier was designed in 0.13μm CMOS process and it can deliver 1.2Vdc for a minimum signal of 1.3Vac. It achieves a power conversion efficiency of 92% at the 13.56MHz…
Read More Development of Miniaturized Monolithic Isolated Gate Driver
Gate driver has been applied in many ways, exemplified by that, by using the DC-isolated and AC-pass characteristics of gate driver’s primary and secondary sides, the problem of floating endpoint in semiconductor power switch can be solved. However, the conventional design of isolated gate driver provides circuit voltage blocking by optically coupled components. Due to…
Read More On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs
This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient…
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