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Keyword: Crosstalk
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Open AccessArticle
6 Pages, 1,518 KB Download PDF

Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

Advances in Science, Technology and Engineering Systems Journal, Volume 3, Issue 1, Page # 109–114, 2018; DOI: 10.25046/aj030113
Abstract:

Through-Silicon-Vias (TSVs) are utilized for high density 3D integration, which induce crosstalk problems and impact signal integrity. This paper focuses on TSV crosstalk characterization in 3D integrated circuits, where several TSV physical and environmental configurations are investigated. In particular, this work shows a detailed study on the influence of signal-ground TSV locations, distances and their…

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(This article belongs to the SP4 (Special issue on Advancement in Engineering Technology 2017-18) & Section Electronic Engineering (EEE))
Open AccessArticle
7 Pages, 1,883 KB Download PDF

Scalability of Multi-Stage Nested Mach-Zehnder Interferometer Optical Switch with Phase Generating Couplers

Advances in Science, Technology and Engineering Systems Journal, Volume 7, Issue 4, Page # 140–146, 2022; DOI: 10.25046/aj070418
Abstract:

A nested Mach-Zehnder interferometer (MZI) configuration whose phase shifters are placed in parallel is suitable for silicon-silica hybrid structure to realize a high-speed optical switch. Even when the signal wavelength deviates from an optimal wavelength, the crosstalk of the nested MZI optical switch can be suppressed by employing phase generating couplers (PGCs) in place of…

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(This article belongs to the SP13 (Special Issue on Innovation in Computing, Engineering Science & Technology 2022) & Section Optics (OPT))
Open AccessArticle
6 Pages, 1,454 KB Download PDF

On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

Advances in Science, Technology and Engineering Systems Journal, Volume 2, Issue 3, Page # 1260–1265, 2017; DOI: 10.25046/aj0203159
Abstract:

This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient…

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(This article belongs to the SP3 (Special issue on Recent Advances in Engineering Systems 2017) & Section Electronic Engineering (EEE))

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